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Title: Parallel Architecture Design And Trade-off Analysis For Hyperspectral Image Processing On Fpga
Authors: Σίμων Βέλλας
Σούντρης Δημήτριος
Keywords: hyperspectral imaging
spectral matching
hardware accelerators
xilinx zynq soc
parallel architectures
Issue Date: 21-Jul-2016
Abstract: In recent years, hyperspectral imaging has found its way in a series of applications ranging from environmental monitoring to high speed sensing and food processing with real time performance. Enhancing the detection abilities of this technology relies on increasing the processing capabilities of the computational units supporting the hyperspectral imaging sensors. In this direction, FPGA-based hardware accelerators have gained the interest of the scientific community due to the very fast processing capabilities as well as the reconfiguration ability offered by this platform. Until today, the efficient programming of these devices is usually done with hardware description languages like VHDL or Verilog.In the current thesis, we developed in parametric VHDL the kernel of a hyperspectral imaging system and we implemented multiple configurations on Zynq-7000 SoC FPGA. From a functional point of view, the developed system matches incoming pixels from a hyperspectral camera with a set of spectral signatures known a priori. We combined various parallel architectures on three abstraction levels and we followed a modular design approach allowing for easy adaptation to algorithm/matching. We evaluated the acceleration of our system and compared it against software implementations on CPUs, e.g. Intel i3 and embedded ARM. Additionally, on MATLAB, we conducted a performance evaluation of the signature matching system with respect to its accuracy; we considered hyperspectral images of up to 285 spectral channels (from various cameras), three matching algorithms/metrics, and we examined the performance by using three quality measures. Based on our study, we provided a trade-off analysis among hardware implementation, system speed and accuracy. In the end, impressive results were achieved even for the most realistic of the considered scenarios: the hardware acceleration ranges from 70x321x (vs. i3-3110Μ) to 626x9694x (vs. ARM Cortex A9), whereas the completeness/correctness/quality of the detection system ranges from 70% to 98% for various objects.
Appears in Collections:Διπλωματικές Εργασίες - Theses

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