Estimating The Failure Probability Of Finfet-based Sram Cells Under Time-zero And Time-dependent Variability

Abstract

Due to the aggressive downscaling of devices, the reliability issue has come to surface. The everlasting demand for the shrinking of dimensions has led to the introduction of the multi-gate, three dimensional FinFET device. The complexity of the new device compared to planar CMOS renders the estimation of the failure probability (PFAIL) of integrated circuits (IC) even more difficult. Themain threat of a system’s reliability is the variability provoked by time-zero phenomena during the manufacturing process and time-dependent effects, with Bias Temperature Instability (BTI) being the dominant one. The model that accurately explicates BTI is the atomistic one which efficiently captures the stochastic nature of this degradation mechanism.Techniques that were widely-used for the evaluation of the PFAIL although they were effective for older technologies, when it comes to modern downscaled devices either require a colossal number of simulations or lead to inaccurate results. Therefore, in this work we focus on the Most Probable Failure Point (MPFP) methodology and we explore the accuracy limits of the standard approach against a state-of-the-art one. We examine the stability of a 6T Static Random Access Memory (SRAM) cell since it is a component highly vulnerable to degradation and we use the Static Noise Margin (SNM) for the hold operation as metric. We compare the results of the two concepts and we verify our claim that the MPFP methodology is much more realistic, using the Monte Carlo technique.