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|Title:||A High Performance Fpga Implementation Of A Feed-forward Carrier-phase Recovery Algorithm For 16-qam Real-time Coherent Receivers|
|Authors:||Κωσταλάμπρος Ιωάννης - Βατίστας|
carrier phase recovery
blind phase search
|Abstract:||The majority of the modern high speed (exceeding 100Gbps) fiber-optic networks utilize bothhigh throughput and higher order modulation schemes to cope with the bandwidth hungry moderntelecommunication needs. A key enabler of such systems is coherent detection and at the heart ofa coherent detection receiver lies the Carrier Recovery sub-module.While the bandwidth efficiency increases a lot with higher constellations usage (16-QAM, 64-QAM, 256-QAM etc) the noise tolerance of the link becomes even more critical and Carrier Recoveryrequires state-of-the-art hardware solutions. Unlike in wireless communications where theCarrier Recovery is accomplished with Digital Phase Locked Loops (PLL) in high speed opticalnetworks there is the need of high-performance and high-parallelism hardware to keep up with theincreased speeds and overcome the barrier of the limited CMOS circuit speeds.The current thesis aims at implementing a high efficiency, feed-forward Carrier Phase Recoveryalgorithm on an FPGA platform, targeted at 16-QAM real-time Digital Coherent Receivers. Thehighly-efficient FPGA platforms give us the opportunity to boost up the speed of our design bysupporting an big external parallelization order.In the beginning, we compare the industry benchmarks Carrier Phase Recovery algorithms(Viterbi-Viterbi, Blind Phase Search) with a less popular but highly-efficient alternative (NLSEstimator). During the comparison stage, we derive its optimal parameters (filter's type, filter'slength) through simulation. To facilitate its efficient hardware implementation we perform a polynomialapproximation on the core element of the algorithm.After implementing the algorithm on the FPGA platform we perform various measurements toevaluate the system's performance and efficiency.From the performance investigation we have found that the NLS Estimator algorithm canbe successfully ported on the Virtex-7 Family FPGA platform and it can provide us with highthroughput beyond 46 Gbaud net rate. The system also exhibits good linewidth tolerance since allof the hardware configurationswe tested presented ...... SNR penalty for 28 GBd and for linewidthbetween 200 kHz and 2 MHz which is a safe margin covering more than the bandwidth of modernExternal Cavity Lases. All things considered our system implementation can support not only thecurrent state-of-the-art networks but also the tomorrow's bandwidth demanding ones (300Gbps+) while yielding efficient performance and increased exibility|
|Appears in Collections:||Διπλωματικές Εργασίες - Theses|
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