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Title: Irregular Network-on-chip Architectures: System-level Exploration And Cad Tools
Authors: Ιάσων - Ιωάννης Φιλιππόπουλος
Σούντρης Δημήτριος
Keywords: network-on-chip (noc)
system level
design flow
application mapping
irregular topologies exploration
buffer sizing
energy optimization
Issue Date: 22-Jan-2010
Abstract: The purpose of the present diploma thesis is the development of a simulation tool that along with a systematic design methodology will perform traffic optimization on network-on-chip topologies. The key metrics are delay and power consumption on the network and simulation results aim to reveal the optimum irregular topology for each traffic scheme.In Chapter 1, we make an introduction to the basic properties and the function of Network-on-Chip. Knowledge presented in this chapter is necessary in order to implement specific methods and techniques for simulation of NoC.In Chapter 2, there is a presentation of design flow for NoC. There is a detailed description of each design stage from application mapping to synthesis and validation of the system. We focus on simulation tools that simplify various stages of the design flow and justify the need for the simulation tool developed in this thesis.In Chapter 3, there is an in depth analysis on the simulation tool implemented. We present its features and extensions, which developed during this work, and also its functionality.In Chapter 4, we present a large number of experimental results based on real applications used in embedded systems.Last, in Chapter 5, we present the findings of this work along with some topics and ideas that need future research and study.
Appears in Collections:Διπλωματικές Εργασίες - Theses

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