Development Of A Design Framework For Power/ Energy Consumption Estimation In Heterogeneous Fpga Architectures

Abstract

The FPGA is an integrated circuit that contains many (64 to over 10,000) logic cells and hard blocks that can be viewed as standard components. The key to Fpgas' popularity is their ability to implement any circuit simply by being appropriately programmed (or reprogrammed). Most current reasonably sized FPGA user designs make use of hard specific-purpose heterogeneous blocks in addition to basic logic and routing fabric. These hard circuits are specific circuits included on an FPGA to perform specific logic functions, such as a multipliers or a memories, which could also be implemented using the base logic units and the routing fabric.In order to investigate the quality of different FPGA architectures, one needs CAD tools capable of automatically implementing circuits in each FPGA architecture of interest. Once a circuit has been implemented in an FPGA architecture, one next needs accurate area, delay and power models to evaluate the quality (speed achieved, area required, power consumed) of the circuit implementation in the FPGA architecture under test. Power is especially a concern in Field-Programmable Gate Arrays (FPGAs). The post-fabrication flexibility in these devices is provided using a large number of prefabricated routing tracks and programmable switches. These tracks can be long, and can consume a significant amount of energy every time they switch. In addition, the programmable switches add capacitance to each track; this further increases the power dissipation of FPGAs. Also the generic logic structures that are at the heart of every FPGA consume more power than the dedicated circuitry that would be found on an ASIC. In this thesis frameworks and tools of FPGA design are analysed and a complete framework its proposed for power estimation in heterogeneous FPGAs, named NAROUTO, along with a Heterogeneity Support Toolset (HST). With this framework one can explore different heterogeneous FPGA architectures in terms of delay , area and power, and the HST toolset can be used in collaboration with other academic tools for further research.