Spartan-3 Fpga With Pci Interface For Mass Memory Pcb-tester

Abstract

The thesis deals with FPGA design. More concretely, a FPGA design is created, which simulates a Microprocessor’s timing. Using this FPGA design, the stimulation of slave PCBs, which are connected on the board is possible. The PCBs are used for real time and long term tests.Inside the FPGA design the module which is implemented can work in two modes, master and slave. In master mode, the signals sent out, will simulate the work of an ERC 32 microprocessor and their values will depend on the input "Assembly type" commands given from the user. These commands are transferred through the PCI Interface to the FPGA. In slave mode, the FPGA design doesn’t simulate any more the work of an ERC 32 microprocessor but it receives signals which are produced by such a microprocessor. It can translate these signals and it can carry out the operation these signals imply.Finally, a user interface is developed, which gives a direct and easy access to the new module, which is implemented inside the FPGA.