Υλοποίηση Με Γλώσσα Περιγραφής Υλικού Vhdl Του Πρωτοκόλλου Συμπίεσης Εικόνας Jpeg-2000 Σε Πλατφόρμα Xilinx Virtex-5

Abstract

The purpose of the present diploma thesis is the co-design and implementation of a Digital Signal Processing (DSP) application on a Xilinx Virtex-5 platform. The DSP application that was selected for this purpose was the JPEG2000 image compression standard. The whole procedure is presented here split in two major parts. In the first part, the methodology that led to a specific hardware/software partitioning strategy is presented, including specification analysis and profiling of JasPer, an open-source software-based implementation of the JPEG2000 codec. A detailed set of timing profiles is presented for the JasPer code. Analysis of these profiles led to the decision of selecting the Inverse Discrete Wavelet Transform for implementation in hardware. Additionally, the first part contains a description of the hardware architecture that was implemented in VHDL and the respective simulation results that followed. Furthermore, the first part includes a presentation of the Xilinx EDK tool set and the JPEG200 co-design architecture. The last chapter of the first part presents the implementation results. In the second part, a step-by-step guide is presented, which allows one to follow all the basic and essential steps in order to integrate the developed VHDL design into a larger System-on-Chip and implement it on a Xilinx Virtex-5 development platform. The system incorporates a MicroBlaze processor and was designed and implemented using the set of tools included in the Embedded Development Kit (EDK), which is provided by Xilinx.