Software Simulation Of Temperature Distribution & Device Degradation Of Integrated Circuits

Abstract

Advances in the modern semiconductor industry give rise to various reliability aspects of electronic design. On the one hand, device behaviour is dominated by stochastic phenomena that may vary even between the devices of the same technology. A timely example of such mechanisms is Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN). On the other hand, the inevitable increase of functional block density in modern integrated circuits makes the temperature distribution a serious design constraint. As a result, fast, yet accurate thermal profiling is of vital importance both at design time and at runtime.The first part of the current work deals with the time and workload dependent device variability of modern downscaled technologies. BTI and RTN are incorporated in circuit simulations of larger circuits, the parametric reliability of which is of major importance. There is a fundamental differentiation from the state of the art, since the atomistic approach towards BTI and RTN allows the observation of detailed workload dependency in the simulation results. This concept is materialized in a fully functional simulation framework of a 32 bit SRAM partition. Based on a real memory architecture, the workload of such a structure was extracted by realistic a realistic application and simulated on the circuit under test. Performance metrics of the circuit, where monitored during the simulation of different workloads. Each different workload, or RunTime Situation (RTS), is instantiated by a cumulative delay metric and a leakage energy value. This concept enables the clustering of RTSs into workload scenarios.The second part of the current work deals with the numerical acceleration of the publicly available thermal simulator HotSpot-5.0. An extensive profiling of its source code, revealed a CPU intensive iterative method for the extraction of the transient solution. This method was replaced with a simplified equivalent that achieved the intended acceleration, without imposing any accuracy degradation. The accelerated version of the tool was successfully incorporated to a broader tool that performs hierarchical thermal profiling of Muli-Processor System-on-Chip (MPSoC) floorplans. That way, the application spectrum of such thermal analysis tools is significantly broadened.