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Title: Power Aware Scheduling On Multicore Systems
Authors: Φοίβος Φιλιππόπουλος
Κοζύρης Νεκτάριος
Keywords: multicore systems
numa architecture
gang scheduling policies
applications/parallel applications
energy consumption
energy optimization
Issue Date: 26-Aug-2013
Abstract: Energy consumption of modern computing devices is becoming an increasingly important topic, especially for battery-powered mobile devices that run on reserved power. As the progress in the field of battery capacity seems unable to follow the increase in processors power needs for performance, power aware scheduling problem has been a recent issue, as it could have a vital role on portable devices running life. Recent commodity processors support multiple operating points running under various supply voltage levels, giving programmers the ability to adjust their system power consumption level according to their current needs. Consequentially, the Dynamic Voltage-Frequency Scaling (DVFS) has become a popular technique and several scheduling algorithms have been developed. Those algorithms are aiming to propose ways to reduce power consumption by imposing appropriate frequency and voltage levels to the system, in order to avoid unnecessary energy expenses.If the Operating System (OS) is aware of the power consumption on the various processes within the system, it can schedule processes based on the constrains derived by the thermal analysis and the remaining power of the system. In addition, OS can balance the resource allocation of each process to remain within a given power envelope. However, obtaining the processor and the system power consumption is a non-trivial task. Existing power meters generally report only the power consumption on the whole system and are unable to provide detailed information for each processor individually. As a result it is very hard to expose a task’s runtime power consumption, if multiple tasks are running in the system at the same time. The estimation of the power consumption on the thread level for every running process is a crucial requirement in designing power efficient schedulers.In this work we analyze the power consumption of the target system, running a Non-Uniform-Memory-Access (NUMA) processor, and formulate a single power consumption model. Then, we examine the relationship between application’s scalability and its power consumption by running our benchmark suite with different thread counts. The importance of the frequency scaling (DVFS) techniques is explored by measuring the performance of each benchmark on all the available frequencies supported by the system. We use Energy Delay Product (EDP) and Energy Delay Squared Product (ED^2 P) as metrics to evaluate our results and create Pareto graphs to reflect our benchmark’s power profile. We choose a suite that includes benchmarks with different characteristics regarding their needs in memory and CPU and use them to compare different proposed scheduling policies. We attempt to reduce the power consumption of the benchmark applications by applying the previous results on them. A significant reduction on the power consumption is shown. Finally, we examine techniques to reduce the cache and background memory conflicts and propose a memory balancing power aware scheduling algorithm.
Appears in Collections:Διπλωματικές Εργασίες - Theses

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