Efficient Estimation Of Reliability Metrics For Circuits In Deca-nanometer Nodes

Abstract

In modern technologies of integrated circuits (IC) and with the downscaling of device dimensions,various degradation modes constitute major reliability concerns. Bias Temperature Instability (BTI)is a representative example, posing as a significant reliability threat in Field-Effect Transistor (FET)technologies and has been known for more than 30 years. At first, the model that tried to explain thisphenomenon was based on the Reaction-Diffusion (RD) theory and was developed nearly 30 yearsago. Recently, an atomistic model has been proposed, that enables the modeling of BTI in moderntechnologies.By observing the amount of software designed to simulate the BTI degradation, tools can be foundthat are based on the atomistic theory but are computationally prohibitive when it comes to simulatingcomplex circuits consisting of a large number of devices. Tools based on the RD model are unableto accurately capture the BTI-induced degradation, especially in devices with small dimensions. Thecurrent thesis is appropriately positioned since it discusses a novel simulation framework that is efficientyet highly accurate. A subset of an embedded Static Random Access Memory (SRAM) is used forverification purposes. The estimation of the functional yield of the circuit over three years of operationwill be examined as well as other reliability metrics, such as defects per million (DPM), mean time tofailure (MTTF) and failures in time (FIT rate). Finally, the interplay between these metrics is discussedand efficient computation methods are proposed for each one.