Acceleration of Neuron Simulation in FPGAs

Abstract

Neuroscience studies the human brain, the nervous system and how it functions and organizes itself. The main focus of these studies are the human brain and how it defines each person's consciousness and behavior. While in the past most of the experiments were done in labs studying small amounts of neurons or the brain itself, nowadays neuroscientists use computers to simulate neuronal networks in great detail, complexity and size. Those simulations also help them keep track of more variables and grant them the ability to visualize large networks, aiding them further in their research. The ever more complex and large neuron networks that neuroscientists want to simulate has generated a need to accelerate neuron simulations in different platforms and architectures. While there are a lot of universal simulators that cover neuroscientists’ basic needs, most of them are not optimized for modern computer systems and consequently don’t achieve the best performance possible, causing the simulations to demand hours or days in execution time, delaying research. This diploma thesis attempts to appease the need for accelerated simulation by utilizing the Maxeler Data Flow Engine platform to accelerate an Adaptive Exponential Integrate-and-Fire neuron model with Spike-timing Dependent Plasticity which is widely used by neuroscientists. The simulation was firstly imported from Brian Simulator to C programing language and then developed for the DFEs. Maxeler DFE platform is built with FPGAs and uses a dataflow graph to process data, decoupling logic from memory. In the DFEs the computation in time is transformed into a computation in space. This implementation was able to accelerate neuron simulation up to x8 times in comparison to the Brian Simulator and is able to simulate networks of more than 20000 neurons, while keeping the same functionality of synapses with the Brian Simulator. However, there was observed a variation in the acceleration rates of the DFEs in comparison to the C and Brian Simulator due to the event-driven architecture of the simulation and the deterministic runtime of the FPGAs. This fact constitutes a point of interest and is investigated further in this diploma thesis.