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|Title:||Design Automation and Synthesis Techniques for Approximate Computing|
|Abstract:||Since the failure of Dennard scaling, energy efficiency has become a first-class design concern in computer systems. Its potential benefits go beyond reduced power demands in servers and longer battery life in mobile devices, since improving energy efficiency has become a requirement due to limits of device scaling and the well-known "dark silicon" or "power wall" problem. Recently, exploiting the intrinsic error resilience of a large number of application domains, approximate computing has emerged as a design alternative for energy efficient system design, trading accuracy for significant energy gains. In this thesis, we focus on the design of hardware approximate accelerators. Approximate hardware circuits, on the contrary to software approximations, offer also transistors reduction, lower dynamic and leakage power, lower circuit delay and opportunity for down-sizing. Existing hardware approximation techniques mainly apply single-level approximation, limiting thus the potential energy-savings of the approximate computing application. Moreover, the increased requirements for verifying the circuit's functionality, as well as operating within the error bounds, greatly increase the design time cycle of approximate hardware accelerators. In this dissertation, in order to max out the benefits of approximate computing application, we examine, introduce, and enable multi-level approximation in the design of hardware arithmetic circuits as well as hardware accelerators. Multi-level approximation refers to applying an approximation technique in every design layer, i.e., the algorithmic, the logic, and the physical ones. However, multi-level approximate architectures exacerbate the design complexity due to the diversity of inexact techniques and their impact on final circuit implementations. In order to enable straightforward and seamless application of approximate computing and multi-level approximation on hardware circuits, we propose four automated frameworks, i.e., VOSsim, Partial Product Perforation framework, HAM, and METHADONE. VOSsim enables very fast and accurate quantification of the power-error characteristics of approximate circuits under voltage over-scaling. Partial Product Perforation is a generalized technique that can be, out-of-the-box, applied to any multiplier circuit, providing known a priori and bound output error values. HAM exploits Partial Product Perforation and introduces multi-level approximation in the design of approximate multipliers, showing that multi-level approximation, compared to single-level one, delivers more efficient solutions in terms of both power and error. Finally, we present METHADONE an approximate accelerator synthesis framework which enables efficient inexact circuits implementations by leveraging the incorporation of diverse multi-level approximate techniques. METHADONE incorporates all the aforementioned frameworks and given the behavioral description of a hardware accelerator and an error bound, quickly produces its power-optimal multi-level approximate counterpart that satisfies the error bound. METHADONE can be applied to any accelerator circuit and seamlessly extends typical behavioral and/or RTL synthesis tools by operating on the accelerator's scheduled data flow graph. The approximate accelerators produced by METHADONE deliver energy savings that range from 10% (for 1% error bound) to 70% (for 10% error bound). Compared to an exhaustive design space exploration METHADONE produces close to Pareto-optimal multi-level approximate accelerators, while delivering more than 589χ speedup in finding the Pareto-front designs. All the proposed frameworks were extensively experimentally evaluated. We demonstrated their efficiency and optimality through comparisons against exhaustive design space exploration and related state-of-the-art works. Specifically, we showed that all the approximate designs produced by the proposed frameworks, outperform existing state-of-the-art designs in terms of both induced error as well as power reduction.|
|Appears in Collections:||Διδακτορικές Διατριβές - Ph.D. Theses|
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|Zervakis-PhDThesis-online.pdf||Georgios Zervakis PhD Thesis||10.08 MB||Adobe PDF||View/Open|
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