DPART: Deterministically Indexed Address Translation with Multiple Page Sizes via Partitioned Address Space

Abstract

Virtual memory has been a vital contribution to computer systems, redefining memory utilization and substantially ameliorating computer programming experience. However, even being an inextricable element of modern architectures, virtual memory’s address translation mechanism presents great performance overheads. To overcome this, we propose DPART (Deterministically Indexed Address Translation with Multiple Page Sizes via Partitioned Address Space). Concretely, our proposed scheme partitions the virtual address space and allocates memory areas accordingly, so that a virtual address’s most significant bits indicate the address’s used page size. Leveraging this feature, we prototype a single set associative TLB structure accommodating translations from all page sizes. In addition, we describe a supporting page table managing to decode translations in less space. Implemented in Linux 4.19, DPART achieves negligible TLB miss rates for most tested configurations and shows superiority against other schemes. Not limited in its TLB performance benefits, DPART characteristics promise low latencies, energy efficiency and reduced chip size.