Please use this identifier to cite or link to this item: http://artemis.cslab.ece.ntua.gr:8080/jspui/handle/123456789/17647
Title: Fast Packet Classification on FPGA using RISC-V and binary search acceleration
Authors: Pnevmatikou, Arsinoi
Σούντρης Δημήτριος
Keywords: RISC-V
FPGA
Network Processors
HW/SW Co-design
Soft-Processor
Hardware Accelerator
Packet Classification
HyperSplit
Binary Search
Issue Date: 23-Mar-2020
Abstract: Performance demands in communications technology is driving research towards advanced network processors, which are able to handle huge rates of incoming packets via application-specific circuits, however, without sacrificing all of the conventional CPU flexibility. At the same time, the advent of RISC-V, an open-source ISA processor developed at UC Berkeley, is disrupting the industry and academia by opening computer architecture to a broader research community, allowing more researchers to explore architectural and implementation issues. Combining the above, the current work considers placing dedicated VHDL accelerators next to a RISC-V processor to accommodate network functions via customized HW/SW co-processing. We deal with the most common and challenging network task, that of Packet Classification, using the HyperSplit algorithm for performance measurements in our research. We extend the instruction subset RV64IAC of the RISC-V ISA with a new instruction that corresponds to the HyperSplit binary search tree operation. For our hardware design we use the rocket chip generator, creating a configuration that includes one RV64IAC RISC-V core and the ability for core-accelerator communication. We create a VHDL HyperSplit search hardware accelerator and we connect it to the main rocket chip RISC-V core using the RoCC interface. For rapid prototyping and design exploration, we implement the binary search of HyperSplit algorithm on an Xilinx Ultrascale xcku060 FPGA. Our VHDL accelerator consumes 5K LUT, 2K DFF, 0 DSP and 570 RAMB (53% of FPGA) for storing data structures with up to 381K nodes. By tuning our pipeline, we achieved fclk= 227MHz for P=5 pipeline stages. Our RISC-V utilizes 15K LUT, 7K DFF, 0 DSP and 5 RAMB and operates at 143MHz. Adding our new accelerator, the design accelerates Packet Classification task, achieving 113x faster classification than RISC-V alone, sustaining up to 25.4M packets/sec throughput (e.g., supporting routers with 8.1Gbps traffic).
URI: http://artemis.cslab.ece.ntua.gr:8080/jspui/handle/123456789/17647
Appears in Collections:Διπλωματικές Εργασίες - Theses

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