Επιτάχυνση μηχανικής μάθησης αλγορίθμων SVM σε πλατφόρμες αναδιατασσόμενης λογικής FPGA

Abstract

The purpose of this diploma thesis is to develop and implement a solution in order to accelerate the machine learning training process of the Support Vector Machines algorithm on Field Programmable Gate Arrays, utilizing High Level Synthesis techniques. A machine learning algorithm is an algorithm that is able to learn from data, i.e improve its accuracy and performance regarding the execution of a given task, after having processed some relevant information. Support Vector Machines (or Support Vector Networks) are supervised learning models with associated learning algorithms that analyze data used for classification, regression analysis and other learning problems. Among their advantages are their high performance and their low need for tuning. One the most popular implementations of an SVM algorithm is offered by the LIBSVM library, which is the base of this diploma thesis. The acceleration of the algorithm is achieved by utilizing the tools the High Level Synthesis offers. HLS is an automated design process that interprets an algorithmic description of a desired behavior in a high-level language and creates digital hardware, commonly for FPGAs that implements that behavior. The goal of the diploma thesis is not the improvement of the implementation of the SVM algorithm by the LIBSVM library, nor the design of specific hardware modules to be used by the algorithm. The goal is the expansion and improvement of the capabilities of the library, in regard to the actual speed of the training process, by exploring the capabilities that HLS offers.