Please use this identifier to cite or link to this item:
|Title:||Computational Methods for Automatic Analog Integrated Circuit Design|
|Keywords:||Analog Integrated Circuits|
automatic circuit sizing
|Abstract:||For decades, the semiconductor and electronics industry have seen great progress, fueled by the continuous scaling of transistor dimensions. Integrated circuits in the sub-μm range have been extensively utilized in the electronics industry. Nowadays, with Moore’s law coming to an end, transistors’ gates have reached unprecedented lengths. The eventual power and speed gains, however, come with an increase in complexity and in design considerations; random variations in the manufacturing process induce variations in circuit device parameters and effectively lead to low-yield designs. Design verification is constantly becoming more cumbersome for circuit design, especially in the case of analog circuits. Circuit designers have traditionally resorted to Electronic Design Automation (EDA) tools for complex circuit design. Given sets of device compact models, named Process Development Kits (PDKs), EDA tools can simulate complex circuits and can be used for verification purposes. In the case of digital circuitry, established EDA tools provide automation solutions for designers to avoid cumbersome, repetitive tasks and focus on the core design. Analog and Radio-Frequency (RF) circuit design, however, has no established means of automation. This thesis presents methodologies for analog and RF circuit automatic sizing. From a high-level perspective, the contributions of this work lie in two factors; 1) The proposal of a family of black-box optimization algorithms, which take advantage of recent machine learning developments to accelerate and improve the exploration of the circuit’s design space, and 2) the development of a framework for procedural simulation execution and optimization definition, based on commercial circuit simulators. The proposed framework exposes a user-friendly Application Process Interface (API) that can be used by designers to execute ad-hoc optimization problems and guide the sizing of their circuit. The first thrust of this thesis is the study of automatic circuit sizing in the context of black-box simulation-driven optimization. We apply and compare black-box optimization algorithms for the nominal sizing of analog and RF circuits, compare their performance and discuss their ability to provide feasible solutions within given evaluation budgets or time-frames. Taking into account that most black-box algorithms operate on continuous spaces, we define a new mutation and crossover operation for Evolutionary Algorithms (EAs) and apply it for circuit sizing. The aforementioned principles are studied for both the case of Single-Objective (SO) optimization and Multi-Objective (MO) one, when design-space exploration and feasible performance space needs to be found. To reduce the cost of optimization in the sense of reducing the number of costly evaluations, we consider next the case of low budget optimization algorithms. In this setting, a new SO Bayesian Optimization (BO) algorithm is introduced. The use of Gaussian Processes (GPs) and a new, batched acquisition function relying on Thompson Sampling (TS) reduces the effective time for each optimization run. Taken into account the fact Gaussian Processes require O(n3) time for inference, kernel approximations are introduced to the GPs by using inducing points. In addition to the above, a new framework is proposed in which the GP models are restricted to model certain hypercubes of the design space. This approach, which is motivated by the concept of trust-regions in the EA literature, provides exquisite constraint-handling capabilities, is scalable in terms of input parameter space and proves favorable against other BO approaches as well as other EA algorithms. To extend the concept of local-based BO in the case of multiple objectives, a new, batched, Local Constrained Multi-Objective Bayesian Optimization (LoCoMOBO) approach is put forward. This MO optimization algorithm not only assists designers to size circuit-blocks, but also to assess the attainable performance metrics of a given topology. LoCoMOBO utilizes trust regions, and uses a Hypervolume-based acquisition function to define future query points for evaluation. In addition, TS is replaced with Random Fourier Features so as to ensure both that the design space is properly explored, in high-dimensional spaces. To efficiently traverse mixed-variable input-spaces, where some parameters are continuous while others are integer-valued or categorical ones, a deep learning scheme that derives continuous representations of integrated devices is put forward. The core model is a Variational Autoencoder (VAE), which uses label guidance to transform the devices’ input parameters to continuous-valued latent ones. The original device parameters are substituted by the VAE’s latent variables in the optimization-based automatic sizing formulation, which is solved using the proposed local-based BO with satisfactory results. In the final chapter, the conclusions of the conducted research are drawn, guidelines for future work are provided and potential impact on industry and society is discussed.|
|Appears in Collections:||Διδακτορικές Διατριβές - Ph.D. Theses|
Items in Artemis are protected by copyright, with all rights reserved, unless otherwise indicated.