Efficient Acceleration of Complex DSP Applications on Reconfigurable Devices: Platform and Architecture Optimizations

Abstract

In recent years, there has been a remarkable surge in the field of embedded systems, especially in the consumer electronics sector. The growing demand for high-performance and energy-efficient systems has motivated researchers to come up with innovative design techniques to meet these challenging requirements. Among various aspects, streaming Digital Signal Processing (DSP) has gained particular attention, involving complex mathematical computations such as matrix inversions, filtering, and basic arithmetic operations. As DSP continues to gain importance in various devices, certain factors like time-to-market and flexibility for late design changes have become critical considerations. Software-based solutions provide flexibility and the ability to make adjustments even in the later stages, but they often lag behind hardware in terms of performance due to the limitations of serial processing. On the other hand, developing custom Application-Specific Integrated Circuits (ASICs) can be a time-consuming process and lacks reconfigurability once the fabrication is completed.

This dissertation revolves around accelerating demanding and complex digital signal processing applications on re-configurable devices, with a particular emphasis on SoC-FPGAs. The applications covered in this research span two domains: image/video processing and telecommunications. In the image/video processing domain, the main focus is on accelerating 1) Medical Imaging and 2) Vision-based navigation applications for space deployments. In the telecom domain, the research centers on low-level physical layer processing, specifically targeting the next-generation 5G/B5G mobile networks. These applications share common characteristics, requiring strict adherence to latency requirements while keeping power consumption at a minimum. To achieve these objectives, extensive Design Space Exploration (DSE) is carried out, and advanced design techniques are employed. The utilization of the unique features of the underlying SoC-FPGA device further enhances the effectiveness of the proposed solutions.