Microarchitectural Approaches to Fault Tolerance in Spaceborne Processors

Abstract

On-board computer systems in space applications -such as satellites or spacecraft- are prone to errors caused by the effects of radiation and thus require increased robustness against faults in order to successfully complete their critical and costly missions. The majority of existing and conventional approaches to fault tolerance use space or time redundancy, resulting in robust designs with high fault coverage. Nevertheless, in these methods, robustness comes at the cost of sacrificing performance, area, and power efficiency, since excessive hardware or execution are duplicated. Therefore, microarchitectural fault tolerance methods have been developed, aiming at reducing the above overheads. This thesis examines such approaches to fault tolerance that leverage microarchitectural insights by comparing 3 methods in various axes. By implementing and evaluating all techniques on a cycle accurate computer system simulator we demonstrate that novel ideas from computer architecture can be utilized to produce more efficient solutions for fault tolerance which also meet the unique requirements of spaceborne systems.