Design and Evaluation of Bespoke Microprocessor Architectures for Flexible Devices

Abstract

In recent years with the rise of power-hungry ML applications, Printed Computing serves to meet the requirements for cost, conformity, and non-toxicity where standard silicon-based computing seems to be lacking. The aspects of low manufacturing costs and disposability that printed technologies provide, fit well with a variety of ML applications’ needs. On top of that, using printed microprocessors allows for programability and thus flexibility to the workloads that can be run, compared to application specific hardware that tends to be more power hungry. Limitations for printed technologies can be extremely large feature sizes along with limited power support from small printed batteries. Hence there is a rising need for improvements in the domains of area and power, in order to fit complex processors. One approach to this issue is hardware reduction techniques, that have shown to be fruitful and necessary when considering printed processors that need to meet constraints. In this thesis we explore the possibilities for area and power gains of printed microprocessors using the EGFET standard cell library for low voltage printing technology, regarding machine learning workloads and printed workloads. We synthesize and analyse hardware measurements for a set of examined processors, focusing mostly on low gate-count and low power architectures. We compile the benchmarks and simulate the processors with RTL and netlist simulations to extract the execution traces using the Synopsys EDA suite and Modelsim simulator. We analyse the execution traces of the workloads to locate and remove unused whole compo- nents and more specific logic functionalities of the ISA of our processors, with the aim of building bespoke processors with improved hardware specs. We then incorporate MAC units that efficiently improve the performance and consumption specifically for ML workloads like MLPs and SVMs with high MAC usage. Finally, we explore the benefits of introducing precision-scaling in our new MAC units, measuring the speedup and accuracy loss tradeoff. Our proposed units and bespoke modifications achieve from 22.2%, 23.6% and 33.79% improvements in area, power and speedup when imposing no accuracy loss, up to 29.3%, 28.7% and 41.73% gains in area, power and speedup, with just a 0.5% decrease in average accuracy estimated over 3 datasets for the main Zero-Riscy Core.