Towards Performance Counter Based Power Modeling - RISC-V ISA Use Case

Abstract

Over the last few years, the energy needs of a typical system are getting bigger. In this scaling situation the need of power management has become a necessity, with almost all the microcontroller families implementing a power model which can predict and, as a result, also manage the power consumption of a end application execution. In this thesis, we propose a close to hardware power-performance measurement of a RISC-V ISA based SoC called RocketChip, which is emulated in the ZC706 FPGA development board, by using the communication protocol with the ARM core of the Zynq SoC and managing to transfer the performance data using the FIFO lists which this protocol implements. With the data gained of this measurement technique we use Spearman correlation and performing static (typical) and cross-correlation with the data gained form 10 different benchmarks, as well as two different denoising algorithms (Rolling Average and Gaussian Filter), we manage to observe the constrains a power model should, which are an application-specific character, it needs to be sequential and to detect non-linear behaviors, to have memory of the past power-performance events and to be scalable among different configurations and frequencies. Finally we came to a conclusion that the already implemented performance counters of the RocketChip need to be expanded in order to cover more building blocks of the SoC system.