Unifying Unary Arithmetic and Hardware-Software Co-design for Efficient Data Processing in Machine Learning Classifiers

Abstract

Machine Learning (ML) applications of Neural Networks (NNs) can benefit from efficient low-cost digital circuit design which allows them to be implemented in printed form. In this work, we investigate the benefits of employing unary arithmetic, as well as other approximation techniques, in performing multiplications, additions and accumulations, for optimized cell area and power consumption. We consider our design near the sensor edge to provide an example bespoke analog-to-digital converter (ADC) that fully harvests the benefits of unary representation. We apply these ideas to suggest digital circuit designs of Multilayer Perceptron Classifiers (MLPCs), a known computationally intensive ML application, tailor-made to respective trained ML models, and we compare our work to conventional and other state-of-the-art architectures of MLPCs. Our proposed designs outperform other approaches by 46% and 39% on average in terms of area and power consumption, with minimal accuracy degradation.