Design and Evaluation of Clustered Processor Architectures

Abstract

Growing computational demands of modern workloads and the need for better application performance, has led designers to focus on increasing the number of cores into a single chip. This multi-core design is highly effective in many applications because it increases thread-level parallelism, improving the overall throughput. However, improving single-thread performance remains crucial, especially for applications with limited parallelism. Since in many scenarios, instruction-level parallelism becomes a bottleneck designers, tried to implement wider designs, with wider instructions windows and widths. This of course came with an important trade-off: wider windows and issue widths typically require more complex control logic, more power consumption, and significantly impact the clock frequency due to the increased complexity and size of the structures. Another approach was introduced in order to avoid the hazards mentioned before, called “clustering”. Clustering, means dividing resources into smaller, independent groups, each handling a subset of instructions with its own set of resources. Using this method could significantly reduce wire delays, helping to preserve high clock frequencies even as the overall system scales. In this thesis, we analyze the limitations of clustering and review steer ing techniques that have been proposed in previous work. Then, we design and implement four instruction steering methods —Round-Robin, Dependency, Dependency-Load, and Loadcut— which, carefully adapted to the specific goals and architecture of our system. We then evaluate these methods through sim ulation using the gem5 simulator and analyze their performance.