Design and Implementation of Power Amplifier in the FR3 Band for Future 5G/6G Applications in 22nm CMOS FD-SOI Technology

Abstract

In this thesis, the analysis, design, and implementation of a two-stage class-B power amplifier operating in the FR3 band is presented. The amplifier is implemented in 22nm CMOS FD-SOI technology. The central frequency is 7.76GHz, while the bandwidth ranges from 7.125GHz to 8.4GHz.

The structure of the thesis is as follows: Initially, the architecture of modern digital transceivers is presented, highlighting the role of the power amplifier. Then, the fundamental definitions of key performance metrics used in telecommunications to evaluate power amplifiers—such as linearity, gain, output power, and efficiency—are discussed.

Subsequently, the S-parameters, stability analysis techniques, and the high-frequency model of the MOS transistor are introduced. This is followed by an overview of basic design principles for power amplifiers and a comparison of the basic amplifier operation classes, which are also implemented and compared using the 22nm CMOS FD-SOI process.

Next, a comparison is made between single-ended and differential topologies. Particular attention is given to addressing the challenge posed by the low nominal Vds of modern silicon technologies, which is mitigated through transistor stacking.

Following that, the topology of the two-stage power amplifier is presented. After the theoretical background has been established, all the design steps for both the power amplifier stage and the driver are thoroughly analyzed, both at the schematic and layout levels.

In the final chapters, the implementation results are presented and directions for future work are proposed.

This thesis serves as a useful introduction to the theory of power amplifiers and can be a valuable guide for those designing a power amplifier for the first time, especially in modern silicon technologies. Detailed design techniques are presented to achieve maximum output power while overcoming the limitations imposed by the low nominal Vds in advanced CMOS processes.