Combining mitigation techniques for fault-tolerant data transfers in soc fpgas

Abstract

The space industry has experienced a transformation in recent years, transitioning from tradi- tional radiation-hardened devices to Commercial Off-The-Shelf (COTS) SoC FPGAs in space missions. This shift is primarily driven by benefits including reduced costs, shorter time-to- market, increased processing performance, and enhanced development flexibility. However, since COTS SoC FPGAs are not specifically designed for the harsh conditions of space, they remain vulnerable to ionizing radiation. While much attention has been given to the vulner- ability of processing elements such as Arm cores and hardware kernels, uncore components, including communication interfaces, are also highly susceptible to radiation-induced faults. Consequently, ensuring data integrity during transfers between the CPU and hardware kernel is challenging. This thesis proposes a comprehensive fault-tolerant architecture specifically tailored for SoC FPGAs, aimed at mitigating Single Event Upsets (SEUs) affecting payload data during data transfers, without altering the system’s functionality or components. The proposed archi- tecture is implemented on the MPSoC UltraScale+ platform, incorporating fault-tolerant mechanisms in both PL and PS subsystems. It integrates mitigation techniques such as Triple Modular Redundancy (TMR) and temporal redundancy within the FPGA fabric, alongside built-in PS fault-tolerant features, notably the dual-core lockstep capability of the ARM Cortex R5 processor. A targeted fault injection campaign, involving fault pruning and saboteur insertion, was conducted to rigorously evaluate the architecture’s resilience and ef- fectiveness. Experimental results demonstrate significant improvements in system reliability without imposing excessive computational or area overhead.