Please use this identifier to cite or link to this item: http://artemis.cslab.ece.ntua.gr:8080/jspui/handle/123456789/19877
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dc.contributor.authorΓαλανόπουλος, Σπυρίδων-
dc.date.accessioned2025-11-03T08:03:14Z-
dc.date.available2025-11-03T08:03:14Z-
dc.date.issued2025-10-29-
dc.identifier.urihttp://artemis.cslab.ece.ntua.gr:8080/jspui/handle/123456789/19877-
dc.description.abstractMemory allocation has become a critical performance and energy bottleneck in modern systems. Each allocation typically requires handling a page fault in software, which involves expensive context switches, pipeline flushes, and execution on power-hungry out-of-order cores. While acceptable for long-running applications, these overheads dominate short-lived and latency-sensitive workloads such as serverless functions, microservices, and LLM inference, where allocation often accounts for more than 30% of total runtime. At the same time, advanced placement policies (e.g., page coloring, NUMA/NUCA-aware allocation) increasingly demand tight coupling between allocation and address translation, as well as responsiveness to runtime conditions—capabilities that are hard to achieve at software timescales. We present a new hardware–software co-design that accelerates and enriches memory allocation by introducing a programmable hardware allocation engine. It allows the operating system to selectively program this engine to handle allocations directly in hardware, bypassing expensive kernel traps. The engine integrates into the memory hierarchy, executes OS-defined policies on page faults, updates translation structures, and adapts placement decisions dynamically using microarchitectural feedback (e.g., DRAM bandwidth, cache occupancy). This enables fast, translation-aware, and runtime-adaptive memory allocation, while retaining OS control over policy. We prototype our proposed design on an FPGA using a modified RISC-V core that runs Linux. Across a range of short-lived and placement-sensitive workloads, our solution accelerates page allocation by 7-15x, improves end-to-end application performance by 77% on average, with negligible hardware cost (1.5% area). This thesis demonstrates that combining OS programmability with hardware acceleration enables memory systems that are both high-performance and highly adaptable to dynamic runtime conditions.en_US
dc.languageenen_US
dc.subjectvirtual memoryen_US
dc.subjectεικονική μνήμηen_US
dc.subjectpage faulten_US
dc.subjectσφάλμα σελίδαςen_US
dc.subjectoperating systemsen_US
dc.subjectλειτουργικά συστήματαen_US
dc.subjectreconfigurable hardwareen_US
dc.subjectεπαναπρογραμματιζόμενο υλικόen_US
dc.subjectaddress translationen_US
dc.subjectμετάφραση διεύθυνσηςen_US
dc.titleΕιδικευμένες Αρχιτεκτονικές για ενεργειακά αποδοτική και έξυπνη εκχώρηση φυσικής μνήμηςen_US
dc.description.pages78en_US
dc.contributor.supervisorΣούντρης Δημήτριοςen_US
dc.departmentΤομέας Τεχνολογίας Πληροφορικής και Υπολογιστώνen_US
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