ML-Assisted HLS exploration for Runtime Orchestration of Cloud FPGAs

Abstract

FPGAs are increasingly being adopted across the edge-to-cloud continuum due to their ability to provide both high performance and energy efficiency. However, their adoption is difficult due to the complexity of design space exploration and inaccuracies in High-Level Synthesis resource estimation tools. FPGA multi-tenancy has been proposed to enhance resource utilization, yet monolithic designs and dynamic workload demands continue to challenge efficient FPGA usage and compliance with Quality of Service requirements. To address these issues, this thesis presents a three-phase methodology for optimizing FPGA orchestration in cloud environments while meeting user demands. At the Offline Phase, we generate bitstreams for every selected design to approach the Pareto-front with actual implementation data, creating a ground-truth dataset that requires months of synthesis time. To reduce the computational strain for future applications, in the ML-Assisted Offline Phase we develop machine learning models that predict resource utilization and performance for new applications, resulting in requiring synthesis for only 38% of the selected designs. The models achieve R2 scores exceeding 0.85 and successfully identify all Pareto- optimal configurations. At the Online Phase we demonstrate our optimized orchestration strategy that includes simulated partial reconfigurable regions. The generated Pareto-front allows the runtime orchestrator to select the most suitable design based on available PR regions and the QoS requirements of each user. Experimental results show that our approach significantly reduces QoS violations across a variety of workloads and baseline mechanisms, maintaining violation rates below 30% even under extreme stress conditions where traditional approaches experience complete failure. This methodology enables cloud providers to offer FPGA acceleration services with predictable performance guarantees without requiring exhaustive exploration of the entire design space, transforming months of characterization into practical deployment timelines.