Design Space Exploration And Synthesis Methodologies For Coarse-grained Reconfigurable Co-processor Architectures

Abstract

Technological advances in micro-electronics, enabled the development of complex embedded computing devices, i.e. mobile phones, digital cameras, etc., which dominate the modern everyday life. Such type of systems usually executes a large but specific set of applications, which combine highly dynamic behavior together with high demands in computing power. The designers have to deal with the increased system complexity, in order to provide design solutions that satisfy a set of stringent functional and financial constraints. Today, it is broadly accepted that without the use of automated tools to optimize the hardware and software system's coefficients, designers are led to the adoption of sub-optimal design solutions. This thesis addresses the above problem by developing a set of methodologies for efficient design space exploration and architectural synthesis for digital signal processing coprocessors. Specifically, the proposed techniques target to (i) the development of customized software solutions for dynamic memory management of multi-threaded applications and (ii) the design of efficient customized and reconfigurable coprocessor architectures.Regarding to the automated design space exploration methodologies, we model and analyze the basic building blocks of multi-threaded dynamic memory management for multi-core platforms with shared memory. We propose new algorithms for exploring and traversing the defined parameter space based on constrained orthogonal design space partitioning, which enables multi-objective optimization and automated code generation of application specific dynamic memory management. In addition, we propose a new approach for defining an extended design space for hardware coprocessor synthesis, which takes into account the combined impact of behavioral-algorithmic and architectural level parameters. New exploration algorithms are developed to enable fast and efficient exploration that converges to more globally optimal design solutions. Regarding to the architectural synthesis of reconfigurable coprocessors, we introduce the Flexibility Inlining technique for designing coarse-grained reconfigurable architectures at the circuit level. The proposed technique exploits the mirror symmetry found in ASIC implementations of arithmetic circuits and through appropriate RTL transformations achieves the design of a new reconfigurable micro-architectural template that exploits in a combined manner the architectural optimizations of horizontal parallelism, vertical parallel and operation chaining. In addition, we present a second micro-architectural template that use advanced arithmetic optimization techniques for designing flexible coprocessor datapaths. Each of the aforementioned reconfigurable architectures is complemented with new high level synthesis algorithms in order to enable automated mapping of applications onto the introduced datapaths.We study the effectiveness of the proposed methodologies through multiple and extensive experimental evaluations of the proposed solutions in comparison with state-of-the-art design solutions. In any case, it seems that the adoption of the proposed methodologies leads to a significant shift of the design solutions towards more efficient implementations.