Fpga Implementation Of Computer Vision Algorithms: Application On Linear Time Selection Algorithm

Abstract

Data intensive applications (e.g. computer vision and data management algorithms) impose considerable performance overheads that rarely are sufficiently implemented onto general-purpose computers. Instead of this, moreadvanced implementation medium are absolutely required in order to support sufficient performance. An example affects the usage of customized hardware accelerators, where the most computational intensive kernels are executed.The goal of this thesis is to provide an efficient hardware/software co-design implementation of such a data intensive algorithm. For this purpose, all the timing critical kernels, as they already derived from profiling procedure, were implemented onto reconfigurable hardware. More specifically, the target reconfigurable medium is a state-of-the-art Xilinx Virtex-6 (xc6vlx240t), whereas regarding the rest kernels (non-timing critical) are actually mapped onto a general-purpose CPU. Even though the introduced solution is applicable to various application intensive applications, at this thesis we are dealing with the implementation of Median algorithm targeting to two different application domains: (i) the implementation of Median filtering targeting to remove impulsive noise from data, and (ii) an algorithm for data querying. Since the scope of this thesis affects the sufficient implementation of this algorithm, in terms both of performance and amount of utilized resources, two different versions of this algorithm were developed. More specifically, the first of them employees the minimum amount of memory blocks, whereas the second one is characterized implementation is very important due to inherent limitation about memory blocks found in FPGAs. Additionally, we have to highlight that based on our exploration results we achieve significant increased performance compared tothe software implementation (C++).