Accelerating the Secure Boot Process in Modern Microcontrollers

Abstract

In modern microcontrollers, the integrity of the system is guaranteed in the secure boot process. Specifically, every piece of the software is covered by the Secure Boot mechanism and is attested to not have been tampered with (maliciously or not). The secure boot step has been implemented to shield systems from various system attacks. However, in modern microcontrollers, this step is typically slow, thus degrading the clients’ quality of service, while also being very safety critical in the automotive domain (e.g., might cause severe road accidents in cars). Even though prior works have tried to improve performance of the secure boot process by proposing probabilistic verification schemes or by running the secure boot step in the background (not in the critical path), they only utilize one core of the system. In contrast, modern architectures comprise multiple cores. which so far remain idle and are not used in the secure boot step. In this work, we accelerate the verification step in the secure boot process in mod- ern microcontrollers by leveraging all the available cores of the underlying hardware. We make two key contributions. First, we extensively characterize and evaluate various cryp- tographic algorithms, which are widely-used in different domains, in the verification step of the secure boot process. Second, we accelerate the secure boot process via two novel verification schemes: i) a parallel deterministic verification scheme and ii) a parallel prob- abilistic verification scheme. Both schemes are running on using all the available cores of the system. We evaluate our parallel verifications schemes in two use case scenarios: i) in a microcontroller manufactured by a lead company tailored for the automotive domain, and ii) the rocket RISC-V chip. We demonstrate that our deterministic parallel scheme provides 3.7x performance improvement in the verification step, and 1.4x performance im- provement in the end-to-end secure boot process over the single core-baseline using 6 cores on the microcontroller designed for automotive scenarios. On the rocket RISC-V chip, our parallel deterministic and probabilistic verification schemes improve performance by 2.2x using 8 cores and by 1.8x cores using 14 cores over the single-core baseline scheme.