Optimized FPGA implementation for Random Forests for Anomaly Detection

Abstract

Industrial facilities have always been the target of attacks in various forms and impact on a social, economic and even political level. The integration of advanced information technologies such as the Internet of Things in such environments has exposed them to security issues of the digital world and have brought forward cyber attacks. A popular strategy to protect industrial facilities from such attacks, is to develop detection algorithms and methods based on machine learning as well as time series analysis. The challenge in this cases is to develop quick, even real-time solutions, that detect and even deter malicious attacks. In this work, we propose FPGA acceleration for a predictive model that detects cyber-physical attacks at a Secure Water Treatment facility (SwaT). Literature shows that Random Forest machine learning models exhibit high accuracy in the detection of such attacks. The goal of the thesis is to accelerate the Random-Forest(RF)-based inference through the use of High Level Synthesis framework Vitis HLS targeting an FPGA device. We propose a hierarchical optimization strategy that targets performance enhancement through the synergy of source code optimization techniques and HLS-inherent parallelization techniques. On a first level, we enable parallelism within the execution of a single Random Forest inference task. On a second level, we explore parallelism across multiple Random Forests by proposing two different architectures: (i) a coarse-grained design that facilitates parallel execution through multiple instances of a single RF design and (ii) a throughput-optimized design that is based on pipelined execution of multiple Random Forest across an array of homogeneous Processing Units. Lastly, these two levels of parallelism are coupled with a precision scaling exploration that achieves further performance enhancement through the execution of less complex operations and efficient resources utilization. The above strategy is further enclosed in an automated framework that performs an exploration over a set of examined parameters and delivers a pareto front with solutions that achieve a trade-off between performance and resources utilization. The generated designs are evaluated against C++ and python inference for various inputs sizes achieving a speedup of almost x20.03.