HW/SW Co-Design and Preprocessing for Accelerating Star Trackers on SoC FPGA

Abstract

In space applications, it is critical to measure the satellite's orientation fast and precisely, which can be only achieved using star trackers. This setup consists of a digital image sensor that captures images of the sky, as well as hardware that detects stars and maps them to known constellations in order to determine the inertial attitude of the satellite. Star detection is a process of high complexity due to large amounts of image data, and thus, it takes significant time to execute, especially when operating on conventional microprocessors. Thus, the need for high performance star trackers leads to the use of FPGAs, which offer great parallelisation opportunities and provide remarkable speedups. Towards increased performance and flexibility, there is also a trend of employing Commercial Off-The-Shelf (COTS) accelerators in space applications. In this thesis, we focus on the implementation of an efficient algorithm for accelerating preprocessing operations of star trackers on COTS SoC FPGAs. More specifically, we develop a HW/SW embedded system for accelerating the preprocessing stages of a star tracker pipeline on Xilinx's Zynq. These stages refer to an image binning kernel that decreases the data volume, and to the detection of clusters from which centroids will be subsequently extracted. The proposed architecture exploits parallelisation at multiple levels via parametric HDL circuit design. The HW/SW co-design integrates the PS and PL parts of Zynq, whose communication is established via AMBA AXI protocols. Our integrated system supports dynamic adjustment to the threshold used in clustering process depending on the noise floor level of the image frame. The proposed design is tested with real images captured on a NASA mission and it is evaluated in terms of performance, resource utilisation and power consumption. A software-oriented approach running on the processing system of the SoC is also developed for comparison purposes with our HW/SW embedded system. Our proof-of-concept implementation accurately detects hundreds of clusters within the image frame while accelerating the execution, resulting to a speedup of 60x compared to the ARM processor, with an estimated increase up to 108x. Hence, the proposed HW/SW co-design achieves real-time performance as it benefits from the FPGA's parallel processing architecture and our custom high- and low-level implementation techniques.