Unifying Software Optimization and Hardware Acceleration Techniques in Telecom Applications

Abstract

In recent years with the development of digital communications, applications for various wireless networks necessitate a single-chip design to meet performance requirements. The Multi-Processor System-on-Chip concept is well suited to facilitate the implementation of various telecommunication algorithms for multiple wireless standards within a single device. In this thesis we explored the benefits from software optimizations as well as hardware acceleration techniques, in the field of digital communications. Regarding the Software Optimizations, the Quadrature Amplitude Demodulation algorithm was implemented on ARM-based embedded platform. We benefited from the use of Single Instruction Multiple Data (SIMD) commands the NEON engine provides (C++ Intrinsics). Furthermore, for two QAM Constellations an approximation technique over the original Demodulation algorithm was proposed, in order to reduce the required arithmetic operations. About the hardware accelerator, a Field Programmable Gate Array (FPGA) based fading channel emu- lator was implemented in VHDL. For the modelling of a fading channel, the input signal has to be processed by a Finite Impulse Response (FIR) Filter, whose coefficients are generated in real time and follow a Normal Gaussian distribution. The evaluation of the aforementioned software implementations was conducted by simulating a Digital Telecommunication chain and taking into account two factors: the execution time and the accuracy of the system with the Bit Error Rate (BER) metric, with and without the use of Forward Error Correction (FEC). In particu- lar, depending on the constellation, our proposed Demodulation implementation, having minimal BER deviations, shows up to 38× speedup over the initial floating point model, and an overall 10-20% improvement for a Receiver Module with FEC decoding. Regarding the Fading Channel emulator, we examined the Probability Density Function (PDF) of the output, while a comparison with a floating-point base model showed negligible loss in precision. Specifically the fixed-point faded symbols present <0.5% Mean Relative Error, while the design is capable of operating at 500MHz frequency.