Design and implementation of image processing algorithms on embedded CPU-GPU-SoC devices

Abstract

Nowadays the ever-increasing advancements in technology has led to the deployment of more complex and computationally intensive image processing algorithms. Many of these algorithms have been adopted in present-day embedded systems targeting a variety of applications such as automotive, 3D navigation, surveillance, etc. However in real-time embedded systems, where latency and power play an important role, software-oriented implementations running on general purpose CPUs may not offer satisfactory solutions. The purpose of this thesis is the design of an image processing system for embedded applications, its deployment on a System-on-Chip (SoC) platform and the evaluation of the developed system. As a case study was selected the Harris Corner Detector algorithm, in a real time system getting the input image from a camera. The thesis focus on the acceleration of the Harris-Corner Detector algorithm on the Tegra X1 GPU SoC. More specifically, we examine different ways of communication between CPU-GPU and various programming techniques on GPU with respect to the execution time and the power consumption. Experimental results show an acceleration of up to x74 compared to a pure software implementation on ARM Cortex A57 using CUDA C. Thus, we can easily implement a real-time corner detection getting the input from the camera, without observing any frames latency. In addition, the thesis focuses to the comparison between CPU-GPU and CPU-FPGA (ZC702) combination for the best acceleration of the application.